Recently, C-PHY was provided to describe a high-speed, rate-efficient PHY, especially suited for mobile applications where channel rate limitations are a factor. In the C-PHY specification, a practical PHY configuration consists of one or more three-wire lanes, each lane has six driven states (also called wire states), the driven state of the lane is changed every driving period, and the signals provided by the three wires of the lane are received using a group of three differential receivers. However, when a state transition of the three-wire lane happens, output signals of the three differential receivers may not have the same timing of the zero-cross point, causing an inter-symbol interference and coding jitter issue in the following data clock recovery operation. Therefore, how to provide a method to eliminate the coding jitter is an important topic.